Key ASIC Provider Completes Two Multi-Million Gate Chips with Synopsys' Physical Compiler; Synopsys' Technology Brings New Level of Productivity and Performance to ASIC Design Flow

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Feb. 25, 2003--Synopsys, Inc. (Nasdaq:SNPS), the world leader in integrated (IC) design software, today announced that Texas Instruments ASIC Division has completed two multi-million gate designs using Synopsys' Physical Compiler(R), a central component of Synopsys' Galaxy(TM) Design Platform. In addition, TI has now integrated Physical Compiler into its standard Pyramid ASIC design flow.

"Working with Synopsys' Physical Compiler increased our productivity, improved performance and accelerated turnaround times for these high-end complex IC devices," said Steve Sutton, vice president of Texas Instruments ASIC Division. "The inclusion of Synopsys' Physical Compiler into our standard Pyramid ASIC methodology gives our customers a clear path to taking advantage of TI's advanced silicon processes."

"TI's expertise in providing advanced solutions is evident in its ASIC design flow," said Jerry Lee, senior vice president and general manager, IC Implementation business unit at Synopsys. "With the addition of Synopsys' Physical Compiler, the Pyramid flow is a great vehicle for TI's ASIC customers who want to boost productivity and accelerate design closure."

Physical Compiler, a key component of Synopsys' Galaxy Design Platform, enables the design of high performance circuits on an accelerated timeframe. By unifying synthesis and placement, Physical Compiler offers designers a faster path to timing closure.

The Galaxy Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling advanced IC design. Anchored by Synopsys' industry-leading IC implementation tools, including Floorplan Compiler, Physical Compiler, Design Compiler(R), PrimeTime(R), Star-RCXT(TM) and the open Milkyway(TM) database, the Galaxy Design Platform incorporates consistent timing, common libraries, delay calculation, and constraints from RTL all the way to silicon. The Galaxy Design Platform significantly reduces design time, decreases integration costs and minimizes the risks inherent in advanced, complex IC design.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for integrated circuit (IC) design. The company delivers technology-leading IC design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and is located in more than 60 offices throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.

Note to Editors: Synopsys, the Synopsys logo, Design Compiler, Physical Compiler and PrimeTime are registered trademarks of Synopsys, Inc., and Milkyway, Galaxy and Star-RCXT are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

CONTACT: Synopsys, Inc.
             Robert Smith, 650/584-1261
             rsmith@synopsys.com
              or
             Edelman Public Relations
             Stephanie Porter, 650/968-4033
             stephanie.porter@edelman.com